module comon(
                input	wire		resetb,
		input	wire		sclk,
		input   wire            oclk,		
		input	wire		set_d_ok,
		input	wire	[15:0]	set_addr,
		input	wire	[7:0]	set_data,
		input   wire            out_en,
		input   wire            vsin,
		input	wire		dmx_w_addr_end,
		
		output  wire            out_clk,
		output  reg            new_out_en,
		output  reg            new_vsin,
		output  reg     [9:0]  div_count_max,
                output  reg     [9:0]  clock_low_time,
                output  reg     [9:0]  div_cnt,                
                output  reg     [9:0]  port_l_unit,
                output  reg     [7:0]  shift_length_per_unit,
                output  reg     [7 :0] chip_type,
                output  reg     [15 :0] config_0,
                output  reg     [15 :0] config_1,
                output  reg     [15 :0] config_2,
                output  reg     [15 :0] config_3,
                output  reg     [15 :0] config_4,
                output  reg     [15 :0] config_5,
                output  reg     [15 :0] config_6,
                output  reg     [15 :0] config_7,
                output	reg	[7:0]	config_8,
                output	reg		d_reverse,
                
		output	wire	[31:0]	tout         
                );
                
//**************************************************************/
//			    �����ź�
//**************************************************************/
assign	tout = 0;

//**************************************************************/
//			    ��������
//**************************************************************/
//*********************�ڲ��Ĵ�������***************************/
always @(posedge sclk or negedge resetb)begin
	if (resetb==0) begin
		div_count_max<=239;//0.625M
		clock_low_time<=119;
		port_l_unit<=0;
		shift_length_per_unit<=2;
		chip_type<=0; 
	        config_0<= 0;
                config_1<= 0;
                config_2<= 0;
                config_3<= 0;
                config_4<= 0;
                config_5<= 0;
                config_6<= 0;
                config_7<= 0;	
                config_8<= 0;
                d_reverse<=0;
	end
	else if (set_d_ok==1 )
                case (set_addr)        
			16'h1000:div_count_max[7:0]<=set_data;
			16'h1001:clock_low_time[7:0]<=set_data;
			16'h1016:port_l_unit[7:0]<=set_data;
			16'h1017:port_l_unit[9:8]<=set_data[1:0];
		        16'h1018:shift_length_per_unit<=set_data;
		        16'h1080:div_count_max[9:8]<=set_data;
			16'h1081:clock_low_time[9:8]<=set_data;
			16'h1082:chip_type<=set_data;
			
			16'h1090:config_0[7:0]	<=set_data;
			16'h1091:config_0[15:8]	<=set_data; 
			16'h1092:config_1[7:0]	<=set_data;
			16'h1093:config_1[15:8]	<=set_data; 
			16'h1094:config_2[7:0]	<=set_data;
			16'h1095:config_2[15:8]	<=set_data; 
			16'h1096:config_3[7:0]	<=set_data;
			16'h1097:config_3[15:8]	<=set_data;  
			16'h109a:config_4[7:0]	<=set_data; 
			16'h109b:config_4[15:8]	<=set_data; 
			16'h109d:config_5[7:0]	<=set_data; 	
			16'h109e:config_5[15:8]	<=set_data;	
			16'h109f:config_6[7:0]	<=set_data; 	
			16'h10a0:config_6[15:8]	<=set_data;
			16'h10a1:config_7[7:0]	<=set_data; 	
			16'h10a2:config_7[15:8]	<=set_data;	
			16'h10a3:config_8[7:0]	<=set_data;

			16'h10a5:d_reverse	<=set_data[0];
		endcase	
end

//**************************************************************/
//			    ʱ�ӷ�Ƶ
//**************************************************************/
reg	out_clk_t;
always @(posedge oclk or negedge resetb)begin
	if (resetb==0) begin
	        div_cnt<=0;
	        out_clk_t<=0;
	end
	else begin
	        if(div_cnt<div_count_max)begin
	                div_cnt<=div_cnt+1;
	        end
	        else begin
	                div_cnt<=0;
	        end
	        if(div_cnt<clock_low_time)begin
	                out_clk_t<=0;
	        end
	        else begin
	                out_clk_t<=1;
	        end	       
	end
end

clkmux	clkmux_inst_out_clk(
	.inclk ( out_clk_t ),
	.outclk ( out_clk )
	);

//**************************************************************/
//			    ֡�źŴ���
//**************************************************************/
reg		vs_flag;
reg	[4:0]	v_count;

always @(posedge out_clk or posedge vsin)
	if (vsin == 1)
		vs_flag <= 1;
	else if (v_count[4] == 1)
		vs_flag <= 0;

always @(posedge out_clk)
	if (vs_flag == 0)
		v_count <= 0;
	else if (v_count[4] == 0)
		v_count <= v_count + 1;

always @(posedge out_clk)
	if (v_count == 1)
		new_vsin <= 1;
	else
		new_vsin <= 0;

//**************************************************************/
//			out_enʱ�����л�
//**************************************************************/
reg             out_en_d0,out_en_d1;

always @(posedge out_clk or negedge resetb)begin
	if (resetb==0) begin
	       out_en_d0<=0;
	       out_en_d1<=0;
	       new_out_en<=0;
	end
	else begin
               
               out_en_d0<=out_en;
	       out_en_d1<=out_en_d0;
	       new_out_en<=out_en_d1;
                                 
	end
end

endmodule